The present invention relates to improved methods for manufacturing integrated circuit devices and more particularity to improved methods related to the manufacture of high performance bipolar transistors fabricated with a BiCMOS and CMOS process.
An accelerating trend in the integrated circuit industry is the merging of analog and digital functions onto the same semiconductor substrate. In addition, transistor components located on these devices are challenged to achieve higher performance characteristics, such as higher cut off frequencies, higher transistor gains, lower collector resistance, etc.
Bipolar junction transistors are one of the older types of transistors which can act either as an amplifier or a switching device and are widely used in discrete circuits as well as integrated circuits. Bipolar junction transistors provide high current drive capabilities, are very useful as a constant current source and as an active load in many analog/digital applications. Bipolar junction transistor characteristics are so well understood, that circuit design using bipolar junction transistors is a relatively easy task. In addition, circuit designs using bipolar junction transistors can obtain performance results that are remarkably predictable and quite insensitive to variations in device parameters. Alternatively, complementary metal-oxide semiconductor (CMOS) devices composed of P and N-channel field effect transistors offer low power consumption, high packing density and dynamic memory storage capabilities.
With the advantages of both bipolar junction and CMOS transistor families in mind, the current industry trend is to incorporate both CMOS and bipolar junction transistors onto the same semi conductor substrate. In this manner the advantages of both families of transistors are realized. However, there are disadvantages to this approach in that as circuit devices are downscaled, bipolar junction transistors become more difficult (and thus more expensive) to fabricate. This is especially true if the device is expected to have high performance (bipolar junction transistor) characteristics and yet incorporate optimized CMOS transistors.
To meet the industry needs, a method for providing high performance bipolar junction transistors in a cost effective manner, when incorporating CMOS transistors on a device needs to be addressed (e.g., a cost effective method to form high performance bipolar junction transistors in a BiCMOS and CMOS process).
One prior art method addressing the cost involved with bipolar junction transistor fabrication on a BiCMOS and CMOS device is illustrated in FIGS. 1A-1D. This process involves the fabrication of vertical bipolar junction transistors within a BiCMOS and CMOS process flow. These transistors are typically fabricated by forming a deep N well 12 within a substrate 10. A P-type collection region 11 is then formed within the deep N-well 12. This act, or event, is followed by the formation of isolation regions 13. All the acts, or events, mentioned so far, are performed using masking operations which would also be utilized during CMOS transistor formation (e.g, at to this point in the BiCMOS and CMOS process, no additional masking operations are required to form a bipolar transistor on the device).
Photoresist 14 is applied to the surface of the device in preparation for a pattern to be formed. This pattern is formed using an extra mask 15 (e.g., a mask not normally used in a BiCMOS and CMOS transistor forming process), which blocks UV radiation and removes exposed portions of the photoresist 14. The pattern is then used to implant an N-type base 16. After this act or event, the pattern is removed (e.g., the photoresist 14 is removed).
Next, N-type base contact 17, P-type emitter 18, and P-type collector contact 19 are formed with source/drain implants using masking operations which are utilized during CMOS transistor formation. Finally an isolation region 20 is formed between the base 17 contact implant and the emitter contact implant 18 in order to provide isolation between the two regions during subsequent metallization connections.
Advantages of this prior art method are the relative low cost since only one extra mask 15 is required to form the base of the transistor, however, this bipolar junction transistor formation method suffers a significant disadvantage in that it has poor performance characteristics. In other words the process is well optimized for CMOS transistors, but not for bipolar junction transistors due to a non-optimized collector region 11. In general, this prior art process suffers from high doping at implant surfaces resulting in low base-collector breakdown voltage, high base-collector capacitance, and low early voltage (e.g., a measure of a transistor""s output node properties and how ideal these properties are when the transistor is used as a current source, proportional to the base collector capacitance). The process also suffers from low dopant concentration at larger depths that results in a high collector resistance and high parasitic transistors gains. Some reasons for these low bipolar junction transistor performance characteristics result from restrictions associated with the BiCMOS and CMOS process (such as the tuning process of the collector for source/drain implants, etc.) and the method""s inability to implant high dopant concentrations deep into the collector region.
A second prior art method results in high bipolar junction transistor performance characteristics, however this method requires extra masking operations (and hence extra costs) as illustrated in FIGS. 2A-2E.
In FIG. 2A, a photoresist 30 is applied to the surface of the device in preparation for a pattern to be formed. This pattern is formed using an extra mask 31 (e.g., a mask not normally used in the BiCMOS and CMOS process), which blocks UV radiation and removes exposed portions of the photoresist 30. The pattern is then used to form a buried P-type collector region 32 using a high energy ion implantation (or another similar method) within a deep N-well 33. The pattern is then removed (e.g., the photoresist 30 is removed).
This act, or event, is followed by the formation of isolation regions 34 (e.g., shallow trench isolation (STI) regions) using techniques which are normally used within a BiCMOS and CMOS transistor formation process. Next, photoresist 45 is applied to the surface of the device in preparation for a second pattern to be formed. This pattern is formed using a second extra mask 36 (e.g., a mask not normally used in a BiCMOS and CMOS process), which blocks UV radiation and removes exposed portions of the photoresist 45. The pattern is then used to form deep P-wells 35 which will couple the P-type collector source/drain contact implants (described below) with the deep buried P-type collector region 32. After this act or event, the pattern is removed (e.g., the photoresist 45 is removed).
Next, photoresist 46 is applied to the surface of the device in preparation to form a third pattern. This pattern is formed using a third extra mask 38 (e.g., a mask not normally used in the BiCMOS and CMOS process), which blocks UV radiation and removes exposed portions of the photoresist 46. The pattern is then used to form a highly doped, N-type base 39 via implantation. After this act or event, the pattern is removed (e.g., the photoresist 46 is removed).
Next, an N-type base contact 40, P-type emitter contact 41, and P-type collector contact regions 42 are formed using masking operations that are utilized to form source/drain regions during CMOS transistor formation. Note that the P-type collector source/drain contact implants 42 are coupled to the buried P-type collector 32 via deep P-wells 35, providing lower transistor collector resistance than the prior art transistor structure of FIG. 1D. Finally an isolation region 43 is formed between the base contact region 40 and the emitter contact region 41, respectively, to provide isolation for subsequent metallization steps.
The process of FIGS. 2A-2E results in a P-type collector region 32 which is well optimized for a vertical PNP bipolar junction transistor, because a vertical dopant profile is achieved which is lightly doped on the surface and heavily doped on the bottom. Because this collector is more heavily doped, it achieves high base-collector breakdown voltage, low base-collector capacitance, and high early voltage. In addition, the profile results in low collector resistance and low parasitic transistor gains. The result is a bipolar junction transistor with good performance properties, but is achieved by using several extra masking operations 31, 36, 38 and therefore is achieved at a much greater expense than the prior art process of FIGS. 1A-1D.
Clearly, the challenge of downscaling bipolar junction transistors in a cost effective manner, with high performance characteristics and incorporating optimized transistors needs to be addressed (e.g., the challenge of forming high performance, low cost, bipolar junction transistors in a BiCMOS and CMOS process). Accordingly, the present invention addresses this need.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a method of fabricating high performance bipolar junction transistors in a BiCMOS and CMOS process without the use of several additional masking steps.
One aspect of the invention comprises the formation of a PNP type bipolar junction transistor fabricated within a BiCMOS and CMOS process. The process begins with forming a deep N-type well within a substrate. Isolation regions and P-type implants are formed using techniques that are common in a BiCMOS and CMOS process.
Photoresist is applied to the device surface and a pattern is formed using UV light (or another similar media) and one extra mask (e.g., a mask not normally used in a BiCMOS and CMOS process). Using this pattern, a heavily doped, P-type collector region is formed, which is different than the P-type implants previously formed (e.g., different dopant concentrations). This collector region is optimized for bipolar junction transistor high performance, for example, by varying the dopant concentration in the region, etc. Next, using the same pattern a heavily doped N-type base is formed within the collector region. Note that only one additional mask used for both the P-type collector formation and the N-type base formation (e.g., the method uses only one extra mask which is not normally used in a BiCMOS and CMOS process). After this act, or event, the pattern is removed (e.g., the photoresist is removed).
Next, N-type base, P-type emitter, and P-type collector contact regions are formed using source/drain implants which are also utilized to fabricate CMOS transistors. In addition, the P-type collector contact implants are coupled to the P-type collector via the P-wells providing lower transistor collector resistance. Finally an isolation region is formed between the base contact implant and the emitter contact implant, as may be desired.
By forming a P-type collector and N-type base in this manner the bipolar junction transistor is optimized (e.g., cutoff frequencies, gains, etc.) for the intended application and yet incorporates much of the standard BiCMOS and CMOS process to minimize cost (e.g., only one additional mask/pattern is required for the bipolar junction transistor formation). In other words the transistor performance parameters are greatly enhanced over transistors that do not have an optimized collector region, yet bipolar transistors formed in this manner are very cost effective to fabricate.
Another aspect of the present invention envisions a bipolar junction transistor formed in the above manner, with the exception that the formation of a deep N-well is omitted. In other words, the bipolar junction transistor formation begins with an N-type substrate, the N-type substrate would perform similar functions to that of the N-type deep well. This aspect of the invention may be employed in instances where the bipolar junction transistor does not require isolation or if the bipolar junction transistor isolation is achieved using an alternate method.
In yet another aspect of the invention, a vertical NPN bipolar transistor is fabricated in a BiCMOS and CMOS flow, forming a N-type collector with the same mask as a P-type base. The process begins with forming a deep P-type well within a substrate. Isolation regions and N-type implants are formed using techniques that are common in a BiCMOS and CMOS process (e.g., all the acts, or events, mentioned so far, are performed using masking operations utilized during the BiCMOS and CMOS process).
Photoresist is applied to the device surface and a pattern is formed using UV light and one extra mask. Using this pattern a heavily doped, N-type collector region is formed, which is different than the N-type implants previously formed (e.g., different dopant concentrations, etc.). This collector region is optimized for bipolar junction transistor high performance, for example, by varying the dopant concentration in the region, etc. Next, using the same pattern, a heavily doped P-type base is formed. Note, that only one additional mask is required when forming the pattern that is used for both the N-type collector formation and the P-type base formation (e.g., the method uses only one extra mask which is not normally used in the BiCMOS and CMOS transistor forming process). After this act, or event, the pattern is removed (e.g., the photoresist is removed).
Next, P-type base, N-type emitter, and N-type collector contact implants are formed using source/drain implants and masking operations which would also be utilized during a CMOS transistor formation process. Note, that the N-type collector contact implants are coupled to the N-type collector via the N-wells providing lower transistor collector resistance. Finally an isolation region is formed between the base contact implant and the emitter contact implant.
By forming a N-type collector and P-type base in this manner, the bipolar junction transistor can be well optimized (e.g., cutoff frequencies, gains, etc.) for the intended application and yet incorporate much of the standard BiCMOS and CMOS process to minimize cost (e.g., only one additional mask/pattern is required for the bipolar junction transistor formation). In other words the transistor performance parameters are greatly enhanced over transistors that do not have an optimized collector region, yet bipolar transistors formed in this manner are very cost effective to fabricate.
In yet another aspect of the present invention a bipolar junction transistor is formed in the above manner, with the exception that the formation of a deep P-well is omitted. In other words, the bipolar junction transistor formation begins with a P-type substrate, wherein the P-type substrate performs similar functions to that of the P-type deep well. This aspect of the invention may be employed in instances where the bipolar junction transistor does not require isolation or if the bipolar junction transistor isolation is performed using an alternate method.
When discussing the various aspects of the invention it should be noted that the invention comprises a method in which a collector is formed which is optimized for high performance, however this collector is not the result of a buried collector process, but rather a process in which the collector is formed in a manner similar to the base formation, even to the point of using the same mask and pattern. Basically, the invention discloses a method in which a customized collector region is formed using a masking operation which can also be used to subsequently form a transistor base, thus achieving high performance characteristics with minimal masking operations (and hence lower costs).
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.